The present invention relates to a virtual machine system and more particularly to a guest machine execution control system suitable for processing guest instructions at high speed.
As shown in U.S. Pat. No. 4,456,954, in the virtual machine system, operation of a virtual machine (hereinafter called VM) starts only after a start interpretive execution instruction (hereinafter called SIE instruction) for indicating execution start of the virtual machine has been executed.
FIG. 2 of the accompanying drawings shows the format of an SIE instruction which designates as operands a state descriptor (hereinafter called SD) on a main storage (hereinafter called MS), by using a base register number field B2 and a displacement field D2. An instruction unit of a central processing unit (hereinafter called CPU) decodes the SIE instruction to read out the respective SD fields from the MS and place the fields in hardware resources of the CPU, thereby permitting the CPU to operate as a guest VM. As the hardware resources in which the SD fields can be placed, there may be mentioned a guest mode latch, a program status word (PSW) register, a control register (CR), a general register (GR), a prefix register, an MS extent register and the like. Thus, the SD describeds the architecture of the guest VM as viewed from the side of a guest instruction. On the other hand, the state of the host is reserved in the CPU.
The guest VM started in response to the SIE instruction continues to emulate a guest program until interruption or interception for control transfer to the VMCP takes place. With the term "interruption", it is intended to mean interruptions such as input/output interruption and external interruption which require the processing by the host. The interception may occur, for example, when an instruction requiring the processing by the host has to be executed. Whether the interception is to be issued or not for some of privileged instructions can be designated by an interception mask field contained in the SD. Upon occurrence of the interruption or interception, operation of the guest VM comes to an end, whereupon the CPU is set to the host mode to be restored to the state ready for executing the SIE instruction.
In a virtual machine system, all or part of the I/O processings by the guest are simulated with the VMCP. Namely, when an I/O activation instruction is designated in a guest program, the guest VM stops its operation and an interception is noticed to the VMCP which then simulates the I/O activation instruction of the guest program to start the I/O processings for a real I/O device. A corresponding I/O interruption instruction is acknowledged by the VMCP according to an I/O mask of the host. The VMCP suspends or holds the guest I/O interruption until the guest I/O mask turns on, whereupon the guest I/O interruption is enabled. Similar processings are performed for some of external interruptions from the guest. In the following description, a term "intervention request" is used for indicating that acknowledgement of a guest interruption by the VMCP has been noticed to the guest and the guest interruption is suspended by the VMCP until the mask of the guest turns on.
In the virtual machine system, an intervention request field is provided in the SD as shown in FIG. 2 for the VMCP to suspend the guest interruption. The intervention request field is constructed of bits each being related to a main cause of an interruption to be suspended. Particularly, it is constructed of an I/O intervention request bit related to an I/O interruption, an external intervention request bit related to an external interruption and the like.
A flow of processing the I/O interruption to be suspended by the VMCP is shown in FIG. 3. At step 28, the VMCP acknowledges an I/O interruption request from a particular guest VM (indicated by guest 1). At step 29, the VMCP sets the I/O intervention request bit, in the intervention request field of the SD, at "1" to suspend the acknowledged guest I/O interruption request. Thereafter, the VMCP continues performing the processings and issues the SIE instruction to activate the guest 1. If the I/O intervention request bit of the SD is "1", the guest 1 stops its operation when the I/O mask (indicated by GPSW(IO)) of the guest PSW becomes "1" and notifies the VMCP of an interception.
In more particular, at step 31 the guest 1 starts executing guest instructions since the GPSW (IO) is 0 in the example shown in FIG. 3. Step 32 indicates that the GPSW (IO) changes from "0" to "1" after execution of a Load PSW (LPSW) instruction by which data read from the main storage at the location designated by the operands of the instruction are loaded in the current PSW register, a Store-Then-OR-System-Mask (STOSM) instruction by which the current system mask is stored in the main storage at the designated location and then data of the instruction are OR-ed with the system mask, a Set-System-Mask (SSM) instruction by which data read from the main storage at the location designated by the operands are set in the system mask, or other instructions associated with the system mask. The condition of interception is satisfied when such a change occurs, whereupon the guest 1 terminates executing the guest instruction and notifies the VMCP of the interception (step 33). The VMCP simulates the I/O interruption of the guest 1 (step 34) to again activate the guest 1 (step 35). The guest 1 resumes the processings after the interruption by the I/O interruption handler.
The VMCP suspends the guest external interruption in the similar manner as above, so that the following description is directed only to the guest I/O interruption.
As seen from step 32 of FIG. 3, if an instruction changing the system mask of the guest VM is executed and the GPSW (IO) changes from "0" to "1", it becomes necessary to judge if operation of the guest VM is to be terminated upon reception of an interception or otherwise to be continued, based on the presence or absence of the I/O intervention request.
FIG. 4 shows the sequence of processing an LPSW instruction. The process sequence will be described by using an LPSW instruction by way of example, the same sequence being applied to other instructions changing the system mask. It is first checked at step 14 if there is an access exception or a designation exception. If a cause of exception is present, an interruption process is performed at step 23. If not present, a flag is initialized (step 15). If the GPSW (IO) to be set newly is "1" (step 16), the intervention request field is read from the SD of the guest VM now in concern (step 17). If the I/O request bit of the read-out intervention request field is "1" (step 18), the flag is set at "1" (step 19). The flag "1" indicates that the condition of issuance of an interception in response to the I/O intervention request has been met. Next, the PSW register is set (step 20). If both the flag and the GPSW (IO) are "1", then an interception process is performed (steps 21, 22). If not, processing the LPSW instruction is terminated.
The occurrence frequency of I/O intervention requests is generally so small that the performance to be achieved by the system takes into consideration the case where an LPSW instruction is executed normally over a process main path including steps 14, 15, 16, 20, 21 and 37 or a process main path including steps 14, 15, 16, 17, 18, 20, 21 and 37. Steps for reading an intervention request field and checking an I/O intervention request bit are provided in addition to those by the host LPSW instruction. Such additional steps involve the overhead of processing a guest instruction.
According to the technique described as above, each time an instruction which changes the guest system mask is executed, it becomes necessary to check the presence or absence of an I/O intervention request and check if the condition of an interception by the I/O intervention request has been met, by referring to the SD on the main storage (or a temporary copy of the SD on the local storage of the CPU). Thus, it poses the problem of substantial decline of the performance of processing an instruction which changes the guest system mask.